1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a power compensation capacitor.
2. Description of Related Art
In recent years, there have been proposed stacked semiconductor devices in which a plurality of semiconductor chips including penetration electrodes are stacked (see Japanese Patent Application Laid-open No. 2011-82450). In a stacked semiconductor device described in Japanese Patent Application Laid-open No. 2011-82450, core chips in which only so-called back-end parts are integrated and interface chips in which so-called front-end parts are integrated are stacked. Electrical connection between the chips is made by penetration electrodes that are provided while penetrating through the chips.
Although the type thereof is different from that of the stacked semiconductor device described in Japanese Patent Application Laid-open No. 2011-92450, in recent years, there have been developed wide I/O semiconductor devices that significantly increase the bit number of data that can be input and output at the same time by stacking a plurality of memory chips that can operate by themselves and by connecting each of chips using penetration electrodes.
Because many data input/output circuits operate at the same time in the wide I/O semiconductor devices, it becomes necessary to provide many power compensation capacitors in the chips in order to sufficiently stabilize a power supply voltage. Therefore, a chip area increases as compared with a chip area of conventional semiconductor chips.